What is RTL encoding in Verilog

Depending on the progress of the ASIC development (specification, verification, evaluation) or the type of circuit to be coded (a complete chip, a single function block, an independent reusable macro or a more or less complex system environment of the circuit to be developed), different ones are used Modeling of the VHDL or Verilog code.

With RTL modeling (Register Transfer Level), the immediate goal is to synthesize this code after completion, i.e. to generate a network list (Gate Level Model) from it. This should then be located on the chip later as the specified overall circuit or as a sub-circuit.
Like behavior modeling, RTL modeling is suitable for simulation. However, not every language element from VHDL or Verilog may be used for RTL modeling (see below). The code structure must also meet certain requirements so that it can be synthesized.

When it comes to behavior modeling, you have different goals compared to the RTL description. This code cannot be synthesized, but on the other hand it can be generated very quickly and is possibly easier to read. The level of abstraction is significantly higher than RTL and allows, for example, file access (read and write), string processing of texts via a simulator, it can wait for keystrokes, create complex variable and constant structures, and, and and ... This listed functions will Of course, a circuit like this cannot easily be achieved.
With a behavior description, for example, various algorithms can be implemented quickly and easily and compared with one another without first specifying the circuit structures down to the last detail. The simulation effort (= simulation time) is very low here, since the level of detail of the circuit is very low.
Typical behavior language elements are:

  • (VHDL)
  • (VHDL)
  • complex mathematical functions (sine, cosine, ...)
  • general file access (read, write)
  • general text and string operations
  • general input operations (keyboard)

Both models are available in the example shown. The counter is coded according to RTL, while the test bench contains behavior structures and components.