What is Static Timing Analysis in VLSI

The Statistical Static Timing Analysis of Gate-Level Circuit Design Margin in VLSI Design

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2011 | OriginalPaper | Chapter

This paper investigated the effect of design margin relaxation on overall circuit performance metrics such as operating frequency, area and power. From the experimental results, by designing the circuit using relaxed design margin, we can reduce the waste of design resources, and gain some advantages by using deterministic design infrastructure which is widely used in modern circuit design. In addition to these, if we apply post-silicon optimization to compensate the yield loss generated by design margin relaxation, the yield of the circuit can be raised to the target timing yield with area and power benefit.

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About this chapter
Title
The Statistical Static Timing Analysis of Gate-Level Circuit Design Margin in VLSI Design
DOI
https://doi.org/10.1007/978-3-642-24097-3_61
Publisher
Springer Berlin Heidelberg

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