What happens if the transmission line is interrupted

EP0588783B1 - Line Equalizer - Google Patents

Line equalizer Download PDF

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Publication number
EP0588783B1
EP0588783B1EP19930890181EP93890181AEP0588783B1EP 0588783 B1EP0588783 B1EP 0588783B1EP 19930890181 EP19930890181 EP 19930890181EP 93890181 AEP93890181 AEP 938588783 B1EP 05
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EP
European Patent Office
Prior art keywords
line
transmission
network component
signal
network
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EP19930890181
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English (en)
French (fr)
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EP0588783A2 (de
EP0588783A3 (en
Inventor
Roland Dipl.-Ing. Bobich
Wolfgang Bodner
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Kapsch AG
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Kapsch AG
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Classifications

    • H-ELECTRICITY
    • H04 — ELECTRIC COMMUNICATION TECHNIQUE
    • H04L-TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25 / 00 — Baseband systems
    • H04L25 / 02 details; Arrangements for supplying electrical power along data transmission lines
    • H04L25 / 03 — Shaping networks in transmitter or receiver, e.g. adaptive shaping networks; Receiver end arrangements for processing baseband signals
    • H04L25 / 03006 — Arrangements for removing intersymbol interference
    • H04L25 / 03012 — Arrangements for removing intersymbol interference operating in the time domain
    • H04L25 / 03114 — Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals

Description

The present invention relates to a remotely adjustable line equalizer located at the end of a transmission line. The invention also relates to network components for tree-structured transmission networks using such line equalizers.
At present, a line equalizer must be set to the frequency and phase response of the transmission line to be equalized on site. In particular in the case of branched transmission networks of great extent, the setting of line equalizers arranged in the network nodes is time-consuming because of the great spatial distances. Such transmission networks equipped with line equalizers are, for example, train radio networks in which voice communication is established with a moving train from a railway line maintenance station via line-bound distribution and connection lines that connect radio systems distributed along the railway line to the maintenance station.
In the following description of the invention, the term “transmission path” refers to a 4-wire line or any wired or wireless 2-directional signal path and “transmission line” refers to a 2-wire line or any wired or wireless 1-directional signal path -Signal path understood. Analogously, the term "free space transmission path" denotes a wireless 2-directional signal path.
At this point it should be mentioned that a communication system for modem-modem connections is known from US Pat. No. 5,052,024, in which the frequency shift of the modem carrier frequency occurring on the transmission path between the modems is recognized in one modem (slave) around the other Modem (master) to offset the carrier frequency sent back accordingly, so that the latter receives the correct carrier frequency and does not have to carry out its own correction. For this purpose, the slave modem contains a detector for a training sequence that is evaluated to calculate the carrier frequency offset. Apart from this, the modem has an adaptive FIR filter in the input section for equalizing the frequency response of the transmission line.
EP-A-0 492 856 also discloses a compensation arrangement for two transceivers with an intermediate telephone transmission line, one transceiver sending a training signal to the other transceiver, which the latter uses to create a filter for pre-distorting the signal from it to the first transceiver the signal to be sent back to compensate for the distortion on the transmission path. The system is based on the assumption that the distortions are the same on the way there and back. Among other things, a chirp is proposed as a training signal.
The present invention aims to provide a remotely adjustable line equalizer that can be used in large-scale transmission networks, u.zw. in each case at the end of a transmission link, and thus enables the network to be set centrally from one point when this has to be adjusted for the first time or adapted to changed or added network components. This goal is achieved with a remotely adjustable line equalizer located at the end of a transmission line, which is characterized by:
  • a signal transmission path with an analog / digital converter, a digital filter loadable with filter coefficients and a digital / analog converter;
  • a frequency response detector which can be connected to the output of the analog / digital converter and which detects the frequency response of a chirp signal fed in at the beginning of the transmission line, determines the filter coefficients for the digital filter (16) from the frequency response and thus controls the coefficient input of the digital filter; and
  • a control sequence detector connected to the signal transmission path, which causes the frequency response detector to be switched on for a predetermined period of time when a control sequence which is fed in at the beginning of the transmission line and which leads the chirp signal is detected.
  • In this way, with appropriate coding of the control sequence, so that only a certain line equalizer in the network responds, it can be prompted from any upstream point in the network to carry out its setting routine with which it adapts the parameters of its filter circuits to the upstream transmission line. The use according to the invention of a chirp signal for measuring the line has the advantage that the entire useful bandwidth can be taken into account and the frequency response evaluation can be carried out with the aid of digital signal processing by a signal processor.
    The frequency response detector can, for example, work according to generally known gradient optimization algorithms, e.g. according to the Wiener filter theory (LMS, RLS algorithms or the like). However, the discrete Fourier transform is preferably used because it represents a method that is stable under all conditions. For this purpose, the digital filter is of a linear type and the frequency response detector has, in series connection, a digital filter with an impulse response equal to the inverse of the undistorted chirp signal, a peak value finder with an interval scanner, the sampling interval of which is symmetrical to the point in time of the peak value and equal to the chirp signal duration, a component for fast Fourier transformation (FFT), a complex divider for element-wise division by specified nominal coefficients and a link for the inverse fast Fourier transformation (FFT). This structure is particularly suitable for implementation on a signal processor.
    In order to compensate for the interference effects introduced by the finite length of the sampling interval, a preferred embodiment of the invention is that the coefficient input of the digital filter is preceded by a multiplier for element-wise multiplication with predetermined window function constants, preferably Hamming window constants.
    If the components of the line equalizer described are implemented with the aid of fixed-point arithmetic units, the correct function of the frequency response detector depends on a sufficient signal level at the input of the line equalizer. For this purpose, the line equalizer preferably has:
  • a controllable amplifier connected upstream of the analog / digital converter; and
  • a line loss evaluation path which can be connected to the output of the analog / digital converter and has a sine signal-adapted filter for a sine signal fed in at the beginning of the transmission line, a rectifier and a low-pass filter, the output of which controls the control input of the amplifier;
  • wherein the control sequence detector causes the connection of the line loss evaluation path for a predetermined period of time from the detection of a second control sequence which is fed in at the beginning of the transmission line and which leads the sinusoidal signal.
  • In this way, a compensation of the general line attenuation can be carried out before the frequency response compensation.
    It is advantageous if the control sequence detector responds to FSK-modulated control sequences transmitted in a frequency band outside the useful signal band and, for this purpose, has a bandpass filter matched to this frequency band with a downstream FSK demodulator. This avoids interference with the useful signal due to the control sequences running in the network. The transmission of the useful signal is only interrupted when a chirp signal is transmitted, which takes about 0.2 s.
    A second aspect of the present invention deals with the creation of network components for tree-structured transmission networks using line equalizers according to the invention. For example, three types of remotely adjustable network components are required to operate the train radio networks currently in use in order to be able to synchronize the entire transmission network from one point:
    • Distribution network components for the network nodes;
    • Intermediate network components for connecting two transmission lines and for coupling these transmission lines to a free space transmission line, the latter generally serving directly to supply a train in a specific track section; and
    • End network components for individual transmission lines and for coupling these transmission lines to further open space transmission lines, the latter also taking over the supply of a certain track section or also serving to forward the signal to other network segments.
    According to the invention, the distribution, intermediate and end network components are constructed in accordance with the measures of claims 6, 7 and 10, respectively.
    In train radio applications, there is also the requirement that several network components, which supply successive track sections of a common railroad area, emit their signals at the same time with the same carrier frequency in the free space (single-wave operation), so that there are no interference effects when receiving signals in the moving train. This requirement must be met in particular by intermediate network components.
    In this way, the signal fed to the free space transmitter of the intermediate network component can be delayed by half the transit time that the signal requires from this network component to the last of the respective single frequency group and back again.
    The start and stop accuracy of the time counter is increased if, according to a preferred embodiment of the invention, a filter with an impulse response equal to the inverse of the undistorted chirp signal and a peak value finder following this filter are connected upstream of the start and stop inputs of the time counter.
    To enable delay compensation between an intermediate network component and a subsequent end network component, the latter is preferably equipped with a control sequence detector that triggers the return of a chirp signal received from an upstream network component as soon as a control sequence fed into the network is detected.
    Each line driver of a network component is preferably equipped with a chirp and sinusoidal signal generator that can be triggered by a control sequence. This means that the chirp or sinusoidal signal can be regenerated in each network component in order to enable the subsequent network component to measure the incoming transmission line undisturbed.
    In order to initiate the compensation of a sub-branching area of ​​the transmission network from a remote point, it is advantageous if each line equalizer has a command sequence detector which triggers a corresponding control sequence upon detection of a command sequence fed into the transmission line relating to it.
    The structural design of a network component is simplified if the line drivers, line equalizers, free space transmitters and receivers of the network components are connected to one another via a data bus carrying all control sequences and a signal bus carrying all useful signals with time division multiplexing for the individual useful signals. The line drivers, line equalizers, free space transmitters and receivers can be prefabricated as modules and optionally combined to form a distributor, intermediate or end network component.
    The invention will now be explained in more detail with reference to exemplary embodiments shown in the drawings, in which:
  • 1 shows the arrangement of the remotely adjustable line equalizer at the end of a transmission line and its general wiring;
  • Fig. 2 is a block diagram of the line equalizer;
  • 3 shows a circuit diagram of a tree-structured transmission network in which line equalizers and network components according to the invention are used;
  • 4 shows a block diagram of a distribution network component,
  • Fig. 5 is a block diagram of an intermediate network component;
  • 6 shows a delay time compensation module of the intermediate network component from FIG. 5;
  • 7 is a block diagram of an end network component;
  • 8 shows the frequency band division between the useful and measurement signal on the one hand and the control signal on the other hand; and the
  • 9 to 13 are frequency response diagrams of signals appearing in the frequency response detector.
  • Fig. 1 shows the arrangement of a line equalizer 1 at the end of a transmission line 2, for example a 2-wire line, which connects a transmitter 3 to a receiver 4. The line equalizer 1 is connected upstream of the receiver 4 and compensates for the frequency response and the attenuation of the line 2 as a function of measurement and control signals that are fed in at the beginning of the line 2 by a suitable device 5.
    In the present embodiment, the line equalizer 1 equalizes the useful signals on the line 2 in the frequency range from 0 to 3,000 Hz and is controlled by control signals which are transmitted in the frequency range from 3,000 to 4,000 Hz. This frequency division into useful signal band 6 and control signal band 7 is illustrated in FIG. 8.
    Serial bit sequences with a baud rate of 60 Hz in FSK modulation are used as control signals, whereby the frequency 3.275 Hz stands for logic 0 and the frequency 3.425 Hz for logic 1.
    Other frequency band divisions or control signal codings are familiar to the person skilled in the art.
    The device 5 for remote control of the line equalizer 1 has a microprocessor 8 for compiling the bit sequences, a downstream FSK modulator 9 and sine and chirp signal generators 10, 11, which are each applied to the transmission line 2 via a time delay element 12, 13 from the microprocessor 8 can be. The time delay ensures that an FSK-modulated control signal leads each sine or chirp signal and puts the line equalizer 1 in readiness for measurement. In readiness for measurement and during the measurement, the line equalizer interrupts the signal transmission to the receiver 4.
    The chirp signal sweeps over the frequency range from 0 to 3,000 Hz in a time of approx. 0.2 s.The ideal frequency response averaged over time of such a chirp signal corresponds to curve part 6 in FIG. 8. The finite length of the chirp signal leads to interference effects in the frequency range, so that the frequency response averaged over time of the chirp signal actually used corresponds to the curve in FIG .
    Fig. 2 shows the block diagram of the line equalizer 1 from Fig. 1. The signal transmission path of the line equalizer consists of a controllable input amplifier 14, a downstream analog / digital converter 15, a linear digital filter 16 downstream of this and a digital / analog output -Converter 17 together. The digital filter 16 is of a linear type with an impulse response of limited length. The filter coefficients are loaded via an input 18 which is connected to the output of a frequency response detector 19-26. The control input of the input amplifier 14 is in turn controlled by the output of a line loss evaluation path 28-30.
    The optional connection of the frequency response detector 19 - 26 or the line loss evaluation path 28 - 30 to the signal transmission path 14 - 17 is effected by a control sequence detector 31 - 33 also connected to the signal transmission path 14 - 17 via a switch 34. The control sequence detector 31 - 33 has an input bandpass filter 31, which extracts the control signal in the range from 3,000 to 4,000 Hz (FIG. 8), and an FSK demodulator 32, which derives control bit sequences for a microprocessor 33 therefrom. If this recognizes a frequency response compensation control sequence addressed to it, then it releases the frequency response detector 19-26 for a predetermined period of time. The latter works as follows:
    The received signal Chirp distorted by the transmission line 2v, which carries the transmitted chirp with it at an as yet unknown point in time, passes through a linear digital filter 19 of finite length N with an impulse response which is equal to the inverse chirp function. The inverse chirp function is the chirp functionO-1which satisfies the following equation:
    where chirpO is the time function of the undistorted chirp signal transmitted by device 5, δ is the Dirac function and * is the convolution operator.
    The signal S therefore occurs at the output of the filter 191 on:
    The filter 19 is followed by a peak value finder 20 which records the point in time mT of the peak value of S1 and supplies it to an interval scanner 21 with an interval width of N samples which are symmetrical at the time mT. The output of the interval scanner 21 therefore carries the finite signal vector of length N:
    The interval width N is chosen to be equal to both the length of the filter 19 and the length of the chirp signal and determines the resolution of the system.
    The signal vector is then fed to a fast Fourier transform (FFT) element 22, which calculates its complex Fourier transform:
    The vector represents the (still with errors) frequency response of the transmission line 2 and is shown in FIG. The vector is then divided element-wise in a divider 23 by a complex correction vector in order to eliminate those edge disturbances which are due to the temporal limitation of the chirp signal usedO can be attributed to:
    The correction vector is shown in FIG. 10 and the adjusted frequency response vector in FIG.
    The adjusted frequency response vector is also divided element by element by a complex setpoint vector (Fig. 12), which represents the ideal or desired frequency response of the transmission line 2:
    The result of this division is the complex vector of the compensation frequency response for the filter 16 and is shown in FIG. The division by the correction vector and by the target vector can take place in one step as a complex element-wise multiplication with a corresponding vector.
    By inverse Fourier transformation in a member 25 for inverse fast Fourier transformation (FFT), the preliminary filter coefficient vector for the compensation filter 16 in the time domain is then obtained from the compensation filter frequency response vector:
    In order to compensate for the errors caused by the finite length N of the system, the vector is weighted in an element-wise multiplier 26 with a window function, e.g. a Hamming window, the coefficients of which are chosen as follows:
    The coefficients for the filter 16 are therefore obtained at the output of the multiplier 26
    The filter coefficients are loaded into the filter 16 via the input 18 and remain stored until the next frequency response compensation.
    The line loss compensation is described below:
    When the control sequence detector 31-33 detects a line loss compensation control sequence relating to it, it connects the line loss evaluation path 28-30 to the signal transmission path 14-17 for a predetermined period of time. This is designed to evaluate a sinusoidal signal that is sent briefly by the device 5 with a defined frequency of e.g. 1 kHz and a defined transmission level of e.g. -6 dBm at 600Ω.
    The received signal ES weakened by the transmission line 2, which carries the transmitted sinusoidal signal with it at an as yet unknown point in time, passes through a signal-adapted filter 28, which only allows the predefined sinusoidal signal to pass:
    where MS is the impulse response of matched filter 28 and SA. whose output signal is. At the output of the filter 28, a threshold value detector (not shown) based on the signal SA. the decision is made as to whether the sinusoidal signal is present, in which case further processing is enabled. The received signal ES is then rectified in a rectifier 29,
    and the rectifier output signal SB. is fed to an FIR low-pass filter 30 with the filter coefficient TP, which determines its rectification value Eff:
    which is proportional to the signal level of the received signal ES. Finally, the controllable amplifier 14 is set as a function of the rectified value Eff.
    3 shows schematically a tree-structured transmission network with distribution network components V, intermediate network components Z and end network components E, which are connected to one another by transmission links, with free space transmission links indicated by arrows emanating from the intermediate and end network components Z, E. The individual network components are equipped with remotely adjustable line equalizers of the type described. To rectify the network shown, corresponding control sequences are sent out from the distribution network component 35 at the tree root and forwarded or distributed by the distribution and intermediate network components in the tree branching direction, each time following the sending of a control sequence a chirp signal is sent by the receiving network component is used to equalize the upstream transmission line. The end network components reflect the control sequences back to the tree root, whereby the network equalization is initiated in the opposite direction. The return control sequences are recognized by the distribution network component 35 at the tree root and are no longer forwarded.
    4 shows the structure of a distribution network component V, with the index A denoting the signal direction from the tree root to the branch and the index B denoting the opposite signal direction. The distribution network component V has a line equalizer 1A. for the transmission line arriving from the tree root, the two line drivers 36A1 and 36A2 controls for two outgoing transmission lines to the tree branches, as well as two line equalizers 1B1 and 1B2 for the transmission lines arriving from the tree branches, which via an addition node 37 share a common line driver 36B. for the transmission line going to the tree root.
    5 shows the structure of an intermediate network component Z. In contrast to the distribution network component, this has instead of the line driver 36A2 a free space transmitter 38 and instead of the line equalizer 1B2 a free space receiver 39.
    According to FIG. 3, a plurality of intermediate network components Z can be assigned to a common reception area 40 into which their free-space transmitters 38 are to emit without mutual time shift. For this purpose, each free space transmitter 38 is preceded by a remotely adjustable time delay circuit 44, which is shown in more detail in FIG.
    The transmission signal of the free space transmitter 38 of the network component 41 (FIG. 3) must be delayed by the signal transit time from the component 41 to the component 43 and the transmission signal of the free space transmitter 38 of the network component 42 by the signal transit time from the component 42 to the component 43.
    Control sequence detectors (not shown) in the network components 41 to 43 use the address of a delay compensation control sequence to determine whether they are at the beginning (41), in the middle (42) or at the end (43) of the receiving area 40 and switch to a corresponding operating mode .
    The control sequence is sent from the initial component 41 to the final component 43 and back again and puts the components in the correct operating mode. The returned control sequence is used by the line equalizer 1B. (FIG. 5) of the incoming transmission line of the intermediate network component 41 in direction B, whereupon it sends a chirp signal generator 45 to the line driver 36A. for the outgoing transmission line in direction A. In accordance with their operating mode, the intermediate network components 42 forward this chirp signal without processing, or the intermediate network component 43 arranged at the end of the receiving area 40 returns it in signal direction B to the initial component 41.
    The time delay circuit 44 of each intermediate network component has a time counter 46 (FIG. 6), the start input 47 of which is connected to the signal path to the line driver 36A. for the outgoing transmission line in direction A and its stop input 48 to the line equalizer 1B. for the incoming transmission line in direction B. The time counter 46 thus counts the time between the transmission of the chirp signal by the line driver 36A. and the arrival of the returning chirp signal in line driver 1B.. Half of this time represents the signal propagation time between this component (41 or 42) and the end component 43. The count output of the time counter 46 is fed via a divide-by-2 divider 49 directly to the control input of a controllable delay element 50, which is supplied to the free space transmitter 38 is connected upstream.
    If the intermediate network component is operating in the end component operating mode (43), its control sequence detector connects the output of the line equalizer 1A. via an internal signal path 56 directly to the input of the line driver 36B.so that the incoming chirp signal is reflected.
    After the chirp signal has passed back and forth, the intermediate network components 41-43 return to normal operation.
    In FIG. 6, the start and stop inputs 47 and 48 of the time counter 46 are preceded by filters and peak value finders, which detect the exact times when the chirp signals occur. The filters 51, 52 correspond to the filter 19 from FIG. 2 and the peak value finders 53, 54 correspond to the peak value finder 20 from FIG. 2, so that reference is made to their description.
    FIG. 7 shows the structure of an end network component E from FIG. 3. The end network component has a line equalizer 1A. for the transmission line arriving from the tree root in signal direction A, which controls a free space transmitter 38, as well as a free space receiver 39, which has a line driver 36B. for the outgoing transmission line in signal direction B to the tree root. Furthermore, a control sequence detector (not shown) is provided which, as soon as a corresponding control sequence is recognized, causes a received chirp signal to be returned via an internal signal path 55.
    The line drivers 36 of the network components V, Z and E are also each equipped with a chirp and sinusoidal signal generator (not shown) which regenerates the measurement signal in the frequency response and line loss compensation modes. In the transit time compensation operating mode of the middle and end components 42, 43, this regeneration does not take place in order not to falsify the measurement of the signal transit time.
    Furthermore, each line equalizer can be equipped with a command sequence detector (not shown) which responds to a specific command sequence directed to it and fed into the network, converts it into a corresponding control sequence and forwards it. As a result, for example, a command sequence can be sent into the network from the distribution network component 35 (FIG. 3), which is only converted into a control sequence in the distribution network component 57 and from there the equalization of the transmission links to the end network components 58 and 59 initiates.
    The discrete functional components shown in the drawings can be implemented in the form of software components, with all components of a line equalizer, a line driver, a free space transmitter or a free space receiver being executed by a microprocessor / signal processor pair. The tasks of the control sequence detector are taken over by the microprocessor, while the tasks of the frequency response detector, the line loss evaluation path, the signal transmission path and the time delay circuit are taken over by the signal processor.
    A microprocessor / signal processor pair, which, depending on the configuration, embodies a transmitter, receiver, driver or equalizer, is connected to the remaining drivers, equalizers, transmitters and receivers of a network component V, Z or E via a common bus system that consists of all control sequences leading data bus and a signal bus leading all useful signals. Each component-internal signal connection is assigned a time slot on the signal bus. The connecting lines shown in FIGS. 4 to 7 between components 1, 36, 38 and 39 therefore correspond to specific time slot assignments. It can be seen that the cross-module cross-connections shown with dashed lines can be established by simple access of one module to the input or output time slot assigned to another module.

    Claims (14)

    1. Remotely adjustable line equalizer (1) which is arranged at the end of a transmission line (2), characterized in that the line equalizer (1) has:
      a signal transmission path (14-17) with an analog / digital converter (15), a digital filter (16) which can be loaded with filter coefficients and a digital / analog converter (17);
      a frequency response detector (19-26) which can be connected to the output of the analog / digital converter (15) and which detects the frequency response of a chirp signal fed in at the beginning of the transmission line (2) and determines the filter coefficients for the digital filter (16) from the frequency response and thus controls the coefficient input (18) of the digital filter (16); and
      a control sequence detector (31-33) connected to the signal transmission path (14-17), which causes the frequency response detector (19-26) to be switched on for a predetermined period of time upon detection of a control sequence which is fed in at the beginning of the transmission line (2) and which leads the chirp signal.
    2. Line equalizer according to Claim 1, characterized in that the digital filter (16) is of the linear type and the frequency response detector (19-26) is connected in series with a digital filter (19) with an impulse response equal to the inverse of the undistorted chirp signal, a peak value finder (20) with interval scanner (21), the sampling interval of which is symmetrized to the point in time of the peak value and is equal to the chirp signal duration, a member (22) for the fast Fourier transform (FFT), a complex divider (23) for element-wise division by predetermined nominal coefficients and a member (25) for the inverse Fast Fourier Transform (FFT).
    3. Line equalizer according to Claim 1 or 2, characterized in that the coefficient input (18) of the digital filter (16) is preceded by a multiplier (26) for element-wise multiplication with predetermined window function constants, preferably Hamming window constants.
    4. Line equalizer according to one of Claims 1 to 3, characterized in that the line equalizer (1) further comprises:
      a controllable amplifier (14) connected upstream of the analog / digital converter (15); and
      a line loss evaluation path (28-30) which can be connected to the output of the analog / digital converter (15) and has a filter (28) adapted to the sine wave signal for a sine wave signal fed in at the beginning of the transmission line (2), a rectifier (29) and a low-pass filter (30) , the output of which controls the control input of the amplifier (14);
      wherein the control sequence detector (31-33) causes the connection of the line loss evaluation path (28-30) for a predetermined period of time from the detection of a second control sequence which is fed in at the beginning of the transmission line (2) and which leads the sinusoidal signal.
    5. Line equalizer according to one of Claims 1 to 4, characterized in that the control sequence detector (31 - 33) responds to FSK-modulated control sequences transmitted in a frequency band outside the useful signal band and, for this purpose, a band-pass filter (31) matched to this frequency band with a downstream FSK demodulator ( 32).
    6. Distribution network component for a node of a tree-structured transmission network with line equalizers according to one of Claims 1 to 5, the distribution network component (V) having such a line equalizer (1A.) for a transmission line arriving from the tree root, each of which has a line driver (36A1, 36A2) controls for one of several transmission lines going out to the tree branches, as well as several such line equalizers (1B1, 1B2) for transmission lines arriving from the tree branches, which have a common line driver (36B.) for a transmission line going to the tree root.
    7. Intermediate network component for switching on between two transmission links of a transmission network with line equalizers according to one of Claims 1 to 5 and for coupling these transmission links to a free space transmission link, the intermediate network component (Z) having such a line equalizer (1A.) for the transmission line arriving from one side, which has a line driver (36A.) for the outgoing transmission line on the other side as well as a free space transmitter (38) controls, and such a line equalizer (1B.) for the transmission line arriving on the other side as well as a free space receiver (39) which has a common line driver (36B.) for the outgoing transmission line on one side.
    8. Intermediate network component according to Claim 7, characterized in that it has a control sequence detector which sends a chirp generator (45) to the line driver (36) as soon as a control sequence fed into the transmission network is detectedA.) for the outgoing transmission line on the other side, and that the free space transmitter (38) is provided with a time counter (46) whose start input (47) is connected to the line driver (36A.) for the outgoing transmission line on the other side and its stop input (48) to the line equalizer (1B.) is connected for the incoming transmission line on the other side and whose count value output controls the control input of a controllable delay element (50) which is arranged in the free space transmitter (38), the intermediate network component (Z) also being equipped with a further control sequence detector, which from the detection of a control sequence fed into the network triggers the return of a chirp signal received from an upstream, similar intermediate network component (Z) or the forwarding to a downstream network component (Z, E).
    9. Intermediate network component according to Claim 8, characterized in that the start and stop inputs (47, 48) of the time counter (46) each have a filter (51, 52) with an impulse response equal to the inverse of the undistorted chirp signal and a peak value finder ( 53, 54) are connected upstream.
    10. End network component for a transmission link of a transmission network with line equalizers according to one of Claims 1 to 5 and for coupling this transmission link to a free space transmission link, the end network component (E) having such a line equalizer (1A.) for an incoming transmission line which controls a free space transmitter (38) and a free space receiver (39) which has a line driver (36B.) for an outgoing transmission line.
    11. End network component according to Claim 10, characterized in that it is equipped with a control sequence detector which, as soon as a control sequence fed into the network is detected, triggers the return (51) of a chirp signal received from an upstream network component.
    12. Network component according to one of Claims 6 to 11, characterized in that each line driver (36) is equipped with a chirp and sinusoidal signal generator which can be triggered by a control sequence.
    13. Network component according to one of Claims 6 to 12, characterized in that each line equalizer (1) has a command sequence detector which triggers a corresponding control sequence when a command sequence relating to it and fed into the transmission line is recognized.
    14. Network component according to one of Claims 6 to 13, characterized in that the line drivers (36), line equalizers (1), free space transmitters (38) and receivers (39) of the network components (V, Z, E) are interconnected via a data bus carrying all control sequences and a signal bus carrying all useful signals is connected with time division multiplex allocation for the individual useful signals.
    EP199308901811992-09-151993-09-10 Line equalizer Expired - LifetimeEP0588783B1 (de)

    Priority Applications (2)

    Application NumberPriority DateFiling dateTitle
    AT1837 / 921992-09-15
    AT183792AAT398660B (de) 1992-09-151992-09-15Line equalizer

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    DE4005130C2 (de) *1990-02-171998-12-24Daimler Benz Aerospace AgProcedure for frequency response compensation of long RF cables and arrangement for carrying out the procedure
    US5841810A (en) *1997-01-301998-11-24National Semiconductor CorporationMultiple stage adaptive equalizer
    US7792184B2 (en) *2003-04-242010-09-07Qualcomm IncorporatedApparatus and method for determining coefficient of an equalizer

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